Depletion-type MOSFET

A slab of p-type material is formed from a silicon base and is referred to as the substrate. The source and drain terminals are connected through metallic contacts to n-doped regions linked by an n-channel. The gate is also connected to a metal contact surface but remains insulated from the n-channel by a very thin silicon dioxide (SiO2) layer. SiO2 is a type of insulator referred to as a dielectric.

There is no direct electrical connection between the gate terminal and the channel of a MOSFET.

It is the insulating layer of SiO2 in the MOSFET construction that accounts for the very desirable high input impedance of the device.

The input resistance of a MOSFET is usually more than that of a typical JFET. Because of the very high input impedance, the gate current IG is essentially 0 A for DC-biased configurations.

Basic Operation and Characteristics

The gate-to-source voltage VGS is set to 0 V and a voltage VDD is applied across the drain-to-source terminals. The result is an attraction of the free electrons of the n-channel for the positive voltage at the drain.

The negative potential at the gate will tend to pressure electrons toward the p-type substrate. Depending on the magnitude of the negative bias established by VGS, a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n-channel available for conduction. The resulting level of drain current ID is therefore reduced with increasing negative bias for VGS.

For positive values of VGS, the positive gate will draw additional electrons from the p-type substrate due to the reverse leakage current and establish new carriers through the collisions resulting between accelerating particles. As the gate-to-source voltage VGS continues to increase in the positive direction, the drain current ID will increase at a rapid rate. Due to the rapid rise, the user must be aware of the maximum drain current rating since it could be exceeded with a positive gate voltage.

For the region of positive gate voltages is often referred to as the enhancement region, with the region between cutoff and the saturation level of IDSS referred to as the depletion region.

Shockley’s equation will continue to be applicable for the depletion-type MOSFET characteristics in both the depletion and enhancement regions.

P-channel Depletion-type MOSFET

The construction of a p-channel depletion-type MOSFET is exactly the reverse of the n-channel depletion-type MOSFET. The terminals remain as identified, but all the voltage polarities and the current directions are reversed.

The drain characteristics would appear exactly as in n-channel depletion-type MOSFET, but with VDS having negative values and VGS having the opposite polarities.

Symbols

  • n-channel Depletion-type MOSFET

  • p-channel Depletion-type MOSFET

Biasing

See FET biasing for the general analysis of all FET amplifiers.

DC Analysis

The similarities in appearance between the transfer curves of JFETs and depletion-type MOSFETs permit a similar analysis of each in the DC domain. The primary difference between the two is the fact that depletion-type MOSFETs permit operating points with positive values of VGS and levels of ID that exceed IDSS.

AC Analysis

The fact that Shockley’s equation is also applicable to depletion-type MOSFETs (D-MOSFETs) results in the same equation for gm. The AC equivalent model for D-MOSFETs is exactly the same as that employed for JFETs.

Links to this page
  • Metal-Semiconductor Field-Effect Transistor (MESFET)

    The drain and transfer characteristics of depletion-type MESFET are so similar to those of the depletion-type MOSFET results in analysis techniques similar to those applied to depletion-type MOSFETs.

    The use of a Schottky barrier at the gate is the major difference from the depletion-type and enhancement-type MOSFETs, which employ an insulating barrier between the metal contact and the n-type channel. The absence of an insulating layer reduces the distance between the metal contact surface of the gate and the semiconductor layer, resulting in a lower level of stray capacitance between the two surfaces. The result of the lower capacitance level is a reduced sensitivity to high frequencies (forming a shorting effect), which further supports the high mobility of carriers in the GaAs material.

  • Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)
  • Enhancement-type MOSFET

    Although there are some similarities in construction and mode of operation between depletion-type and enhancement-type MOSFETs, the characteristics of the enhancement-type MOSFET are quite different. The transfer curve is not defined by Shockley’s equation, and the drain current is now cut off until the gate-to-source voltage reaches a specific magnitude.

    As VGS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current. However, if we hold VGS constant and increase the level of VDS, the drain current ID will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. The leveling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel.

    If VGS=0 V and voltage applied between the drain and the source of the n-channel enhancement-type MOSFET, the absence of an n-channel will result in a current of effectively 0 A, which is quite different from the depletion-type MOSFET and JFET, where ID=IDSS.

    In every other aspect, the AC analysis is the same as that employed for JFETs or D-MOSFETs.

    The construction of an enhancement-type MOSFET is quite similar to that of the depletion-type MOSFET, except for the absence of a channel between the drain and source terminals.

#transistor #fet #mosfet