Multiplexers

The circuit consists of four \(D\) flip-flops and four multiplexers. The four multiplexers have two common selection inputs \(\mathrm{S0}\) and \(\mathrm{S1}\). The selection inputs control the mode of operation of the register. When \(\mathrm{S0} = 0\) and \(\mathrm{S1} = 0\), the present value of the register is applied to the \(D\) inputs of the flip-flops. This condition forms a path from the output of each flip-flop into the input of the same flip-flop so that the output recirculates to the input in this mode of operation, creating the effect of a suspended clock. When \(\mathrm{S0} = 0\) and \(\mathrm{S1} = 1\), a shift-left operation results, with the serial input transferred from \(DL\) input into \(\mathrm{Q3}\) output. When \(\mathrm{S0} = 1\) and \(\mathrm{S1} = 0\), a shift-right operation results, with the serial input transferred from \(DR\) input into \(\mathrm{Q0}\) output. Finally, when \(\mathrm{S0} = 1\) and \(\mathrm{S1} = 1\), the binary information on the parallel input lines \(\mathrm{D0}\) through \(\mathrm{D3}\) is transferred into the register simultaneously during the next clock edge.