Digital Logic Gates

In gate-type asynchronous systems, the storage elements consist of logic gates whose propagation delay provides the required storage.

The storage capability of a time-delay device varies with the time it takes for the signal to propagate through the device. In practice, the internal propagation delay of logic gates is of sufficient duration to produce the needed delay, so that actual delay units may not be necessary.

In its broadest definition, a register consists of a group of flip-flops together with gates that affect their operation. The flip-flops hold the binary information, and the gates determine how the information is transferred into the register.

An active-HIGH input \(S\)-\(R\) (set-reset) latch is formed with two cross-coupled NOR gates. When output \(Q = 1\) and \(\bar{Q} = 0\), the latch is in the set state. When output \(Q = 0\) and \(\bar{Q} = 1\), the latch is in the reset state.

An active-LOW input \(\bar{S}\)-\(\bar{R}\) (set-reset) latch is formed with two cross-coupled NAND gates. When output \(Q = 1\) and \(\bar{Q} = 0\), the latch is in the set state. When output \(Q = 0\) and \(\bar{Q} = 1\), the latch is in the reset state.

It consists of the \(\bar{S}\)-\(\bar{R}\) latch and two additional NAND gates. The control input \(EN\) acts as an enable signal for the other two inputs. When the enable input \(EN\) goes to \(1\), information from the \(S\) or \(R\) input is allowed to affect the latch. The control input disables the circuit by applying \(0\) to \(EN\), so that the state of the output does not change regardless of the values of \(S\) and \(R\). Moreover, when \(EN = 1\) and both the \(S\) and \(R\) inputs are equal to \(0\), the state of the circuit does not change.

The De Morgan (complement) equivalent of \(S\)-\(R\) NOR latch.

The De Morgan (complement) equivalent of \(\bar{S}\)-\(\bar{R}\) NAND latch.

The simplified expressions produced by the map are always in one of the two standard forms: sum-of-products (SOP) or product-of-sums (POS). This expression produces a circuit diagram with a minimum number of gates and the minimum number of inputs to each gate.

The propagation delay (or gate delay) is the length of time which starts when the input to a logic gate becomes stable and valid to change, to the time that the output of that logic gate is stable and valid to change.

This standard type of expression results in a two-level structure of gates.

A construction of a \(D\) flip-flop with two \(D\) latches and an inverter. The first latch is called the master and the second the slave. The circuit samples the \(D\) input and changes its output \(Q\) only at the negative edge of the clock \(CLK\). The value that is produced at the output of the flip-flop is the value that was stored in the master stage immediately before the negative edge occurred.

Flip-flops that read in new value on the positive and negative edge of the clock are called dual-edge-triggered flip-flops. Such a flip-flop may be built using two single-edge triggered \(D\) flip-flops and three XOR gates.

It is also possible to design a circuit so that the flip-flop output changes on the positive edge of the clock. This happens in a master-slave \(D\) flip-flop that has an additional inverter between the \(CLK\) terminal and the junction between the other inverter and input \(EN\) of the master \(D\) latch. Such a flip-flop is triggered with a negative pulse, so that the negative edge of the clock affects the master and the positive edge affects the slave and the output terminal.

The term flip-flop has historically referred generically to both level-triggered (asynchronous, or transparent) and edge-triggered (synchronous, or clocked) circuits that store a single bit of data using gates. The terms edge-triggered, and level-triggered may be used to avoid ambiguity.

The \(T\) flip-flop can be constructed using a \(D\) flip-flop and an XOR gate. The \(D\) input is expressed as

The logic diagram of a combinational circuit has logic gates with no feedback paths or memory elements.

When a Boolean expression is implemented with logic gates, each term requires a gate and each variable within the term designates an input to the gate. A literal is a single variable within a term, in complemented or uncomplemented form.